Field effect transistors (FETs) are included in semiconductor chips for a vast variety of semiconductor device applications. For example, in motor drivers, DC-converters and rectifiers, FETs are used as semiconductor switches in a half-bridge configuration that includes a low-side switch and a high-side switch. In view of further developments of these applications, there is a need for increasing the integration level while ensuring appropriate device characteristics.
These solutions are frequently construed with discrete chips having a low-side switch and a high-side switch with a charge pump, or with discrete components in a common housing. In the case of variants with discrete chips, the leakage inductance is frequently disadvantageously high due to the relatively long connections, which causes high switching losses. Integrated discrete chips in a common housing reduce this problem, however, there is still a need for a further reduction of the leakage inductance.
It is common to build a half bridge employing an n-channel MOSFET as a low-side switch and a p-channel MOSFET or n-channel MOSFET with a charge pump as the high-side switch. If the bridge is built into in a common housing, the power switches, in the case of two n-channel transistors in the BE, have to be bonded separately onto the leadframe. This leads to increased costs per package.
In the case of a half bridge with a p-MOSFET as the high-side switch, the separation of the leadframe is not necessary, however, two chips require significantly more space and also cause higher costs for the assembly.
For these and other reasons there is a need for the present invention.